1. Field of the Invention
This invention relates generally to computer readable memory devices, and, more specifically, to methods for reducing noise when reading their information content.
2. Background Information
In non-volatile semiconductor memories, such as EEPROMs, the amount of data stored per memory cell has been increased in order to increase storage densities. At the same time, the operating voltages of such devices have decreased to reduce power consumption. This results in a greater number states stored in a smaller range of voltage or current values. As the voltage or current separation between data states decreases, the effects of noise become more significant in the reading of these cells. For example, variations in the threshold value acceptable in a binary storage, 5 volts EEPROM cell may no longer be acceptable in a device operating at 3 volts with four or more bits storable per cell. Some consequences of noise, and methods for dealing with it, in a non-volatile memory are described in U.S. Pat. No. 6,044,019, which is hereby incorporated by reference.
An example of noisy behaviour is shown in FIG. 1A, which is adapted from U.S. Pat. No. 6,044,019. This figure shows the variation in the current flowing through a memory cell in response to a particular set of bias conditions. The current fluctuates by an amount ΔI due to various noise effects in the memory cell and interfacing circuitry. If, for example, the memory circuit works by current sensing, as the separation between states approaches ΔI, the noise will begin to produce erroneous read values. Although the consequences of noise can be decreased by integration sensing techniques, such as those in U.S. Pat. No. 6,044,019, or treated with error correction code (ECC) or other equivalent error management, such as is described in U.S. Pat. No. 5,418,752, which is hereby incorporated herein by this reference, memories could benefit from further methods to reduce the effects of noise on memory operation.